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rev.4.00 jun. 04, 2004 page 1 of 15 hd74lv161a synchronous 4-bit binary counter (direct clear) rej03d0319?0400z (previous ade-205-264b (z)) rev.4.00 jun. 04, 2004 description the hd74lv161a is 4-bit binary counters. all flip flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. these counters ma y be preset using the load input. presetting of all four flip flops is synchronous to the rising edge of clock. when load is held low counting is disabled and the data on the a, b, c and d inputs is loaded into the counter on the rising edge clock. if the load input is taken high before the positive edge of clock, the count operation will be unaffected. low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. features ? v cc = 2.0 v to 5.5 v operation ? all inputs v ih (max.) = 5.5 v (@v cc = 0 v to 5.5 v) ? all outputs v o (max.) = 5.5 v (@v cc = 0 v) ? typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) ? typical v oh undershoot > 2.3 v (@v cc = 3.3 v, ta = 25c) ? output current 6 ma (@v cc = 3.0 v to 3.6 v), 12 ma (@v cc = 4.5 v to 5.5 v) ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) HD74LV161AFPEL sop?16 pin(jeita) fp?16dav fp el (2,000 pcs/reel) hd74lv161arpel sop?16 pin(jedec) fp?16dnv rp el (2,500 pcs/reel) hd74lv161atell tssop?16 pin ttp?16dav t ell (2,000 pcs/reel) note: please consult the sales office for the above package availability.
hd74lv161a rev.4.00 jun. 04, 2004 page 2 of 15 function table inputs outputs clr load enp ent clk qa qb qc qd lxxxxllll hl xx abcd hhxl no change hhl x no change hhhh count up hxxx no change note: h: high level l: low level x: immaterial : low to high transition : high to low transition a, b, c, d: data input carry = ent ? qa ? qb ? qc ? qd pin arrangement 13 14 11 12 15 16 9 10 v cc carry output qa qb qc qd 1 2 3 4 5 6 7 8 clr ck a b c d enp gnd ent load (top view)
hd74lv161a rev.4.00 jun. 04, 2004 page 3 of 15 absolute maximum ratings item symbol ratings unit conditions supply voltage range v cc ?0.5 to 7.0 v input voltage range* 1 v i ?0.5 to 7.0 v h or l ?0.5 to v cc + 0.5 output: h or l output voltage range* 1, 2 v o ?0.5 to 7.0 v v cc : off input clamp current i ik ?20 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 25 ma v o = 0 to v cc continuous current through v cc or gnd i cc or i gnd 50 ma 785 sop maximum power dissipation at ta = 25c (in still air)* 3 p t 500 mw tssop storage temperature tstg ?65 to 150 c notes: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. the input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 5.5 v maximum. 3. the maximum package power dissipation was calculated using a junction temperature of 150c. recommended operating conditions item symbol min max unit conditions supply voltage range v cc 2.0 5.5 v input voltage range v i 05.5v output voltage range v o 0v cc v ? ?50 av cc = 2.0 v ??2 v cc = 2.3 to 2.7 v ??6 v cc = 3.0 to 3.6 v i oh ? ?12 ma v cc = 4.5 to 5.5 v ?50 av cc = 2.0 v ?2 v cc = 2.3 to 2.7 v ?6 v cc = 3.0 to 3.6 v output current i ol ?12 ma v cc = 4.5 to 5.5 v 0 200 v cc = 2.3 to 2.7 v 0 100 v cc = 3.0 to 3.6 v input transition rise or fall rate ? t / ? v 020 ns/v v cc = 4.5 to 5.5 v operating free-air temperature ta ?40 85 c note: unused or floating inputs must be held high or low.
hd74lv161a rev.4.00 jun. 04, 2004 page 4 of 15 logic diagram output q a clk enable p t a b data inputs c d clr load d ck q clr q output q b d ck q clr q output q c d ck q clr q output q d carry output d ck q clr q
hd74lv161a rev.4.00 jun. 04, 2004 page 5 of 15 timing diagram 12 13 14 15 0 count preset (load) clear inhibit 12 load data inputs a b c d q a q d q c q b clk ent carry enp clr out puts
hd74lv161a rev.4.00 jun. 04, 2004 page 6 of 15 dc electrical characteristics ta = ?40 to 85c item symbol v cc (v) * min typ max unit test conditions 2.0 1.5 ? ? 2.3 to 2.7 v cc 0.7 ? ? 3.0 to 3.6 v cc 0.7 ? ? v ih 4.5 to 5.5 v cc 0.7 ? ? 2.0 ? ? 0.5 2.3 to 2.7 ? ? v cc 0.3 3.0 to 3.6 ? ? v cc 0.3 input voltage v il 4.5 to 5.5 ? ? v cc 0.3 v min to max v cc ? 0.1 ? ? i ol = ?50 a 2.3 2.0 ? ? i ol = ?2 ma 3.0 2.48 ? ? i ol = ?6 ma v oh 4.5 3.8 ? ? i ol = ?12 ma min to max ? ? 0.1 i ol = 50 a 2.3 ? ? 0.4 i ol = 2 ma 3.0 ? ? 0.44 i ol = 6 ma output voltage v ol 4.5 ? ? 0.55 v i ol = 12 ma input current i in 0 to 5.5 ? ? 1 av in = 5.5 v or gnd quiescent supply current i cc 5.5 ? ? 20 av in = v cc or gnd, i o = 0 output leakage current i off 0??5 av i or v o = 0 v to 5.5 v input capacitance c in 3.3 ? 1.7 ? pf v i = v cc or gnd note: for conditions shown as min or max, use the appr opriate values under recommended operating conditions.
hd74lv161a rev.4.00 jun. 04, 2004 page 7 of 15 switching characteristics v cc = 2.5 0.2 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) 50 90 ? 40 ? c l = 15 pf maximum clock frequency fmax 30 60 ? 25 ? mhz c l = 50 pf ? 11.1 16.2 1.0 19.5 c l = 15 pf t plh /t phl ? 14.3 19.2 1.0 22.5 c l = 50 pf clk q ? 11.5 17.0 1.0 20.5 c l = 15 pf t plh /t phl count mode ? 14.7 20.0 1.0 23.5 c l = 50 pf clk carry ? 13.8 20.6 1.0 24.5 c l = 15 pf t plh /t phl load mode ? 17.0 23.6 1.0 27.5 c l = 50 pf clk carry ? 10.3 15.7 1.0 19.0 c l = 15 pf t plh /t phl ? 14.0 18.7 1.0 22.0 c l = 50 pf ent carry ? 11.7 17.0 1.0 20.5 c l = 15 pf t phl ? 14.7 20.0 1.0 23.5 c l = 50 pf clr q ? 11.2 16.6 1.0 20.0 c l = 15 pf propagation delay time t phl ? 14.4 19.6 1.0 23.0 ns c l = 50 pf clr carry 7.5 ? ? 8.5 ? data before clk 10.0 ? ? 11.5 ? load before clk 9.5 ? ? 11.0 ? ent, enp before clk setup time t su 4.5??4.5 ? ns clr inactive before clk hold time t h 1.5??1.5 ? ns 7.0 ? ? 7.0 ? clk h or l pulse width t w 7.0??7.0 ? ns clr l
hd74lv161a rev.4.00 jun. 04, 2004 page 8 of 15 switching characteristics (cont) v cc = 3.3 0.3 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) 80 130 ? 70 ? c l = 15 pf maximum clock frequency fmax 55 85 ? 50 ? mhz c l = 50 pf ? 8.3 12.8 1.0 15.0 c l = 15 pf t plh /t phl ? 10.8 16.3 1.0 18.5 c l = 50 pf clk q ? 8.7 13.6 1.0 16.0 c l = 15 pf t plh /t phl count mode ? 11.2 17.1 1.0 19.5 c l = 50 pf clk carry ? 11.0 17.2 1.0 20.0 c l = 15 pf t plh /t phl load mode ? 13.5 20.7 1.0 23.5 c l = 50 pf clk carry ? 7.5 12.3 1.0 14.5 c l = 15 pf t plh /t phl ? 10.5 15.8 1.0 18.0 c l = 50 pf ent carry ? 8.9 13.6 1.0 16.0 c l = 15 pf t phl ? 11.2 17.1 1.0 19.5 c l = 50 pf clr q ? 8.4 13.2 1.0 15.5 c l = 15 pf propagation delay time t phl ? 10.9 16.7 1.0 19.0 ns c l = 50 pf clr carry 5.5 ? ? 6.5 ? data before clk 8.0 ? ? 9.5 ? load before clk 7.5 ? ? 9.0 ? ent, enp before clk setup time t su 2.5 ? ? 2.5 ? ns clr inactive before clk hold time t h 1.0 ? ? 1.0 ? ns 5.0 ? ? 5.0 ? clk h or l pulse width t w 5.0 ? ? 5.0 ? ns clr l
hd74lv161a rev.4.00 jun. 04, 2004 page 9 of 15 switching characteristics (cont) v cc = 5.0 0.5 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) 135 185 ? 115 ? c l = 15 pf maximum clock frequency fmax 95 125 ? 85 ? mhz c l = 50 pf ? 4.9 8.1 1.0 9.5 c l = 15 pf t plh /t phl ? 8.7 10.1 1.0 11.5 c l = 50 pf clk q ? 4.9 8.1 1.0 9.5 c l = 15 pf t plh /t phl count mode ? 6.4 10.1 1.0 11.5 c l = 50 pf clk carry ? 6.2 10.3 1.0 12.0 c l = 15 pf t plh /t phl load mode ? 7.7 12.3 1.0 14.0 c l = 50 pf clk carry ? 4.9 8.1 1.0 9.5 c l = 15 pf t plh /t phl ? 6.4 10.1 1.0 11.5 c l = 50 pf ent carry ? 5.5 9.0 1.0 10.5 c l = 15 pf t phl ? 7.0 11.0 1.0 12.5 c l = 50 pf clr q ? 5.0 8.6 1.0 10.0 c l = 15 pf propagation delay time t phl ? 6.5 10.6 1.0 12.0 ns c l = 50 pf clr carry 4.5 ? ? 4.5 ? data before clk 5.0 ? ? 6.0 ? load before clk 5.0 ? ? 6.0 ? ent, enp before clk setup time t su 1.5 ? ? 1.5 ? ns clr inactive before clk hold time t h 1.0 ? ? 1.0 ? ns 5.0 ? ? 5.0 ? clk h or l pulse width t w 5.0 ? ? 5.0 ? ns clr l operating characteristics c l = 50 pf ta = 25c item symbol v cc (v) min typ max unit test conditions 3.3 ? 17.0 ? power dissipation capacitance c pd 5.0 ? 20.4 ? pf f = 10 mhz
hd74lv161a rev.4.00 jun. 04, 2004 page 10 of 15 noise characteristics c l = 50 pf ta = 25c item symbol v cc (v) min typ max unit test conditions quiet output, maximum dynamic v ol v ol (p) 3.3 ? 0.3 0.8 v quiet output, minimum dynamic v ol v ol (v) 3.3 ? ?0.3 ?0.8 v quiet output, minimum dynamic v oh v oh (v) 3.3 ? 3.0 ? v high-level dynamic input voltage v ih (d) 3.32.31??v low-level dynamic input voltage v il (d) 3.3??0.99v test circuit l * 1. c includes the probe and jig capacitance. note: measurement point c l
hd74lv161a rev.4.00 jun. 04, 2004 page 11 of 15 waveforms clk 50%v cc 50%v cc 50%v cc 50%v cc v cc t wh t plh t phl t wl gnd v oh v ol q, carry count mode load a~d clk 50%v cc 50%v cc 50%v cc 50%v cc 50%v cc 50%v cc v cc t su t h t plh, t phl t su t h t su t h gnd v cc gnd v oh v ol q, carry preset mode waveform ? 1 waveform ? 2
hd74lv161a rev.4.00 jun. 04, 2004 page 12 of 15 50%v cc v cc t su t h gnd q ck enp ent v cc gnd v oh v ol 50%v cc 50%v cc 50%v cc t su t h count enable mode 50%v cc 50%v cc 50%v cc v cc t wl t phl t su gnd clr clk q, carry v cc gnd v oh v ol clear mode waveform ? 3 waveform ? 4
hd74lv161a rev.4.00 jun. 04, 2004 page 13 of 15 ent carry 50%v cc 50%v cc 50%v cc 50%v cc v cc t plh t phl gnd v oh v ol cascade mode (set to maximum count number) waveform ? 5 1. input waveform: prr 1 mhz, zo = 50 ? , t 3 ns, t 3 ns note: rf application h: count l: disable h: count l: disable clr clk ld a b c d clr enp ent carry output inputs ck qa qb qc qd ld a b c d clr enp ent carry output inputs ck qa qb qc qd ld a b c d clr enp ent carry output inputs ck qa qb qc qd to next stages cascade circuitry
hd74lv161a rev.4.00 jun. 04, 2004 page 14 of 15 package dimensions package code jedec jeita mass (reference value) fp-16dav ? conforms 0.24 g *ni/pd/au plating *0.20 0.05 *0.40 0.06 0.12 0.15 m 2.20 max 5.5 10.06 0.80 max 16 9 1 8 10.5 max + 0.20 ? 0.30 7.80 0.70 0.20 0 ? ? 8 ? 0.10 0.10 1.15 1.27 as of january, 2003 unit: mm package code jedec jeita mass (reference value) fp-16dnv conforms conforms 0.15 g *ni/pd/au plating 1.27 16 9 1 8 0.15 0.25 m 1.75 max 3.95 *0.20 0.05 9.9 0 ? ? 8 ? 10.3 max + 0.10 ? 0.30 6.10 + 0.67 ? 0.20 0.60 + 0.11 ? 0.04 0.14 *0.40 0.06 0.635 max 1.08 as of january, 2003 unit: mm
hd74lv161a rev.4.00 jun. 04, 2004 page 15 of 15 package code jedec jeita mass (reference value) ttp-16dav ? ? 0.05 g *ni/pd/au plating 0.50 0.10 0? ? 8? *0.15 0.05 6.40 0.20 0.10 1.10 max 0.13 m 0.65 18 16 9 4.40 5.00 5.30 max 0.07 +0.03 ?0.04 0.65 max 1.0 * 0.20 0.05 as of january, 2003 unit: mm
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